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Backend Overall Introduction

The backend is the backend of the XiangShan processor, which includes multiple components such as Instruction Decode (Decode), Rename (Rename), Dispatch (Dispatch), Schedule (Schedule), Issue (Issue), Execute (Execute), Writeback (Writeback), and Retire (Retire), as shown in 此图.

Backend Overall Framework

Basic Technical Specifications

  • 6-wide Decode, Rename, and Dispatch
  • 224-entry Integer Register File, 192-entry Floating Point Register File, 128-entry Vector Register File
  • Move Elimination
  • Instruction Fusion
  • 160-entry ROB
  • Supports ROB compression (up to 6 uops per entry)
  • Up to 8 entries retired per cycle
  • Snapshot Recovery
  • Rename Buffer
  • 256-entry RAB
  • Instruction Commit and Register Writeback
  • Integer, Floating Point, and Vector Computation