CtrlUnit Submodule Documentation

Currently, the CtrlUnit is mainly responsible for ECC error checking enable/error injection and other functions.

mmio-mapped CSR

The CtrlUnit implements a set of mmio-mapped CSRs, connected on the tilelink bus. The address can be configured by the parameter cacheCtrlAddressOpt, with a default address of 0x38022080. The total size is 128B.

When the parameter cacheCtrlAddressOpt is None, the CtrlUnit will not be instantiated. In this case, ECC error checking is enabled by default and cannot be disabled by software; software cannot control error injection.

The currently implemented CSRs are as follows:

              64     10        7         4         2        1        0
0x00 eccctrl   | WARL | ierror | istatus | itarget | inject | enable |

              64 PAddrBits-1               0
0x08 ecciaddr  | WARL |       paddr        |

CSR	field	description
eccctrl	enable	ECC error checking enable, originally sfetchctl(0)
eccctrl	inject	ECC error injection enable, writing 1 starts injection, reads always 0
eccctrl	itarget	ECC error injection target, see table below
eccctrl	istatus	ECC error injection status (read-only), see table below
eccctrl	ierror	ECC error reason (read-only), only valid when eccctrl.istatus===error, see table below
ecciaddr	paddr	ECC error injection physical address

eccctrl.itarget:

value	target
0	metaArray
2	dataArray
1/3	rsvd

eccctrl.istatus:

value	status
0	idle
1	working
2	injected
7	error
3-6	rsvd

eccctrl.ierror:

value	error
0	ECC not enabled (i.e. !eccctrl.enable)
1	inject target SRAM invalid (i.e. eccctrl.itarget==rsvd)
2	inject target address (i.e. ecciaddr.paddr) not in ICache
3-7	rsvd

Error Checking Enable

The eccctrl.enable bit of the CtrlUnit is directly connected to the MainPipe, controlling ECC checking enable. When this bit is 0, the ICache does not perform ECC checking. However, it will still calculate and store the parity code during refill, which may incur a small amount of extra power consumption; if it does not calculate, then the ICache needs to be flushed when transitioning from disabled to enabled (otherwise the read parity code might be incorrect).

Error Injection Enable

The CtrlUnit internally uses a state machine to control the error injection process. Its status (note: different from eccctrl.istatus) includes:

• idle: Injection controller is idle
• readMetaReq: Sends a read request to metaArray
• readMetaResp: Receives response from metaArray
• writeMeta: Writes to metaArray
• writeData: Writes to dataArray

When software writes 1 to eccctrl.inject, the following simple checks are performed. If the checks pass, the state machine enters the readMetaReq state:

• If eccctrl.enable is 0, reports error eccctrl.ierror=0
• If eccctrl.itarget is rsvd(1/3), reports error eccctrl.ierror=1

In the readMetaReq state, the CtrlUnit sends a read request for the set corresponding to the ecciaddr.paddr address to MetaArray and waits for handshake. After handshake, it transitions to the readMetaResp state.

In the readMetaResp state, the CtrlUnit receives the response from MetaArray, checks if the ptag corresponding to the ecciaddr.paddr address hits. If it does not hit, reports error eccctrl.ierror=2. Otherwise, based on eccctrl.itarget, it enters the writeMeta or writeData state.

In the writeMeta or writeData state, the CtrlUnit writes arbitrary data to MetaArray/DataArray and simultaneously asserts the poison bit. After the write is complete, the state machine enters the idle state.

A Mux is implemented in the ICache top level. When the CtrlUnit's state machine is not idle, the read/write ports of MetaArray/DataArray are connected to the CtrlUnit, instead of MainPipe/IPrefetchPipe/MissUnit. When the state machine is idle, the opposite is true.