IFU Sub-module PreDecoder
Function Description
Function Overview
The pre-decoder PreDecoder accepts initial instruction codes and performs instruction code generation. Each instruction code queries the pre-decode table to produce pre-decode information. The pre-decode information includes whether this position is the start of a valid instruction, the CFI instruction type, whether it is an RVC instruction, whether it is a Call instruction, and whether it is a Ret instruction. The pre-decoder generates two vectors indicating valid instruction starts: one defaults the first two bytes as the start of a valid instruction, and the other defaults the second two bytes as the start of a valid instruction. The final selection is made in the IFU.
Detailed Feature Description
Feature 1: Instruction Code Generation (instr_gen)
The pre-decoder accepts 17×2 bytes of initial instruction code that has been segmented by the IFU. Using a 4-byte window and a 2-byte step length, starting from the first two bytes up to the 16th two bytes, it selects a total of 16 4-byte instruction codes.
Feature 2: Valid Instruction Start Vector Generation (vec_gen)
While generating the initial instruction codes, the pre-decoder also generates a 16-bit valid instruction start vector. Each bit in this vector identifies whether the instruction at this position is the start of a valid instruction. The generation logic is as follows:
- Normal mode: The first two bytes are defaulted as the start of the first instruction. If the (n-1)-th two bytes are the start of a valid instruction and are an RVC instruction, or if the (n-1)-th two bytes are not the start of a valid instruction (which must be the trailing two bytes of a 4-byte instruction), then the n-th two bytes are the start of a valid instruction.
- Abnormal mode: The first two bytes are defaulted as the latter half of a 4-byte instruction, and the first valid instruction starts from the second two bytes. The subsequent generation logic is the same as in normal mode.
The results for the two modes are generated in parallel, and the final selection is made by the IFU based on whether there is an RVI instruction spanning a cache line.
Feature 3: Pre-decode Information Generation (decoder)
The pre-decoder generates pre-decode information based on the instruction codes, primarily including: whether it is an RVC instruction, whether it is a CFI instruction, the CFI instruction type (branch/jal/jalr/call/ret), and the target address calculation offset for CFI instructions. CFI instruction types are shown in Table 1.2.
Overall Block Diagram
Interface Timing
Since the PreDecode module consists entirely of combinatorial logic, inputs and outputs are available within the same clock cycle.
IFU Sub-module PredChecker
Function Description
Function Overview
The branch prediction checker PredChecker receives prediction block information from the IFU (including the position of the predicted jump instruction within the prediction block, the predicted jump target, instruction information obtained from pre-decode, instruction PC, and jump target offset obtained from pre-decode, etc.). Within the module, it checks for five types of branch prediction errors. The module is divided into two pipeline stages, outputting information separately. The first stage outputs to the F3 stage for correcting the instruction range and prediction results of the prediction block. The second stage outputs to the WB stage to generate a frontend redirect and write back the correct prediction information to the FTQ when a branch prediction error is detected.
Detailed Feature Description
Feature 1: Jal Instruction Prediction Error Check
The condition for a jal instruction prediction error is that there is a jal instruction in the prediction block (given by pre-decode information), but either no jump is predicted for this prediction block, or the predicted jump instruction in this prediction block is after this jal instruction (i.e., this jal instruction is not predicted to jump).
Feature 2: Ret Instruction Prediction Error Check
The condition for a ret instruction prediction error is that there is a ret instruction in the prediction block (given by pre-decode information), but either no jump is predicted for this prediction block, or the predicted jump instruction in this prediction block is after this ret instruction (i.e., this ret instruction is not predicted to jump).
Feature 6: Re-generate Valid Instruction Range Vector
When the PredChecker detects a Jal/Ret instruction prediction error, it needs to re-generate the valid instruction range vector. The valid range is truncated to the position of the Jal/Ret instruction, and all subsequent bits are set to 0. It should be noted that errors in both jal and ret instructions will cause the instruction valid range to be shortened, so the valid instruction range needs to be re-generated as fixedRange, and the prediction result needs to be fixed (i.e., the original prediction result is canceled, and the prediction result for this instruction block is re-generated based on the position of the jal instruction).
Feature 3: Non-CFI Prediction Error Check
The condition for a non-CFI prediction error is that the instruction predicted to jump is shown by the pre-decode information not to be a CFI instruction.
Feature 4: Invalid Instruction Prediction Error Check
The condition for an invalid instruction prediction error is that the position of the predicted instruction is shown by the instruction valid vector in the pre-decode information not to be the start of a valid instruction.
Feature 5: Target Address Prediction Error Check
The condition for a target address prediction error is that a valid jal or branch instruction is predicted, and the predicted jump target address does not match the jump target calculated from the instruction code.
Feature 5: Graded Output of Check Results
The PredChecker check results described above are output separately in two stages. As mentioned earlier, Jal/Ret instructions require re-generating the valid instruction range vector and re-specifying the predicted position, so the results are output directly to the Ibuffer in the cycle the error occurs (F3) for timely correction of instructions entering the backend. Due to timing considerations, other error information (such as the location of the five types of errors, the correct jump address, etc.) is returned to the IFU in the next cycle (WB stage) for frontend redirection.
Overall Block Diagram
Interface Timing
As shown in the figure, yellow represents the checking process for the same prediction block within the PredChecker. The 6th byte position of this prediction block is predicted as a jump. The original valid instruction range for this prediction block is h7f (i.e., 0000000001111111), and the instruction valid vector is hbfeb (i.e., 1011111111101011). However, the checker finds that the position of the 1st byte (counting from 0) in this prediction block is a jal instruction (brType value is b10). Therefore, the checker first modifies the valid instruction range to h3 and the predicted byte position to 1 in stage1, sending this to F3 for Ibuffer instruction enqueue selection. Simultaneously in the WB stage, the target address is corrected to h80002120, the mispredicted position is marked as 6, and the WB stage is notified to perform a redirect.