Load Memory Access Pipeline LoadPipe
Functional Description
This component uses a pipeline to control the processing of Load requests. It is tightly coupled with the Load memory access pipeline and reads the target data or returns a miss/replay response through a 4-stage pipeline.
Feature 1: LoadPipe Pipeline Stage Functions:
- Stage 0: Receives the virtual address calculated by the pipeline in the LoadUnit: reads tag and meta based on the address;
- Stage 1: Obtains the query results for the corresponding tag and meta; receives the physical address from the LoadUnit and performs a tag comparison to determine if it hits; reads data based on the address; checks for
l2_error; - Stage 2: Obtains the corresponding data results; if it's a load miss, sends a miss request to the MissQueue and attempts to allocate an MSHR entry; returns the response for the load request to the LoadUnit; validates
tag_error; - Stage 3: Updates the replacement algorithm state; reports 1-bit ECC check errors to the bus error unit (including data errors found by the dcache, tag errors found by the dcache, and existing errors in the data block obtained from L2).
Overall Block Diagram
The overall architecture of the LoadPipe is shown in 此图.
Interface Timing
Request Interface Timing Example
As shown in 此图, req1 is received by the LoadPipe in the first cycle, reading meta and tag; in the second cycle, tag comparison determines a miss; in the third cycle, the response is returned to the LSU, with lsu_resp_miss asserted high indicating no hit and data cannot be returned for now, and a miss request is sent to the MissQueue simultaneously; in the fourth cycle, ECC errors are checked and reported. req2 and req3 are issued immediately after req1, also received in stage_0, reading meta and tag; in the second cycle, a hit is detected, and a data read request is issued; in the third cycle, data is obtained, and a response with the load data is returned to the LSU; in the fourth cycle, PLRU is updated, and ECC errors are reported.
