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Store Data Execution Unit StdExeUnit

Function Description

The scalar store instruction data pipeline, used for writing store data to the corresponding position in the StoreQueue.

Overall Block Diagram

StdExeUnit Overall Block Diagram

Interface Timing

Interface Timing Example

StdExeUnit Valid Request Interface Timing

As shown in Figure \ref{fig:LSU-StdExeUnit-Timing}, after io_ooo_to_mem_issueStd_0_ready and io_ooo_to_mem_issueStd_0_valid handshake high, a valid write request is received, and the data is io_ooo_to_mem_issueStd_0_bits_src_0. The figure above illustrates writing to the sqIdx0 entry of the StoreQueue at the third clk, with data src0. At the fourth clk, io_ooo_to_mem_issueStd_0_ready is low, and data is not written to the StoreQueue at this time. This situation usually occurs when a vector store instruction needs to write data to the StoreQueue.