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Level 3 Module Hypervisor Page Table Walker

Hypervisor Page Table Walker refers to the following module:

  • HPTW hptw

Design Specifications

  1. Supports accessing G-stage level 3 page tables
  2. Supports sending requests to memory
  3. Supports sending refill signals to the Page Cache
  4. Supports exception handling
  5. Special handling for bypass

Functionality

Supports accessing G-stage level 3 page tables

The overall design of HPTW is basically the same as PTW. It can only process one request at a time, and HPTW can perform a complete translation of the second stage level 3 page table. During the translation process, if memory access is required, a PMP check will be performed on the memory access address. If the check fails, it returns directly; otherwise, it sends a memory access request. HPTW returns under the following circumstances:

  1. A leaf node is reached
  2. A pagefault or accessfault occurs during access

Supports sending requests to memory

Similar to PTW and LLPTW, HPTW needs to send requests to memory when accessing page tables. Requests are sent via an arbiter.

Sends refill signals to the Page Cache

After HPTW receives the result from PTW, it sends a refill request to the Page Cache, filling the returned page table entry into the Page Cache. HPTW will provide the information to be filled into the Page Cache.

Exception Handling Mechanism

When an exception like pagefault or accessfault occurs, HPTW returns directly to PTW or LLPTW.

Special Handling for Bypass

For bypass requests, we usually put them into the MissQueue for re-querying. However, for hptw requests (i.e., isHptwReq is valid), they are not put into the MissQueue (to avoid blocking). Therefore, when a bypass request occurs, to prevent duplicate page table entries from being filled into the Page Cache, if the bypass signal is valid when an hptw request is input to HPTW, the result returned by memory when sending a request to memory will not refill the Page Cache.

Overall Block Diagram

The state transition diagram of the HPTW is shown in 此图.

Hypervisor Page Table Walker state machine state transition diagram

The descriptions of the states in the state machine are as follows:

  • idle: The initial state of the Hypervisor Page Table Walker state machine. After receiving a PTW request, it enters the pmp_check state.
  • pmp_check: In this state, the physical address to be accessed is sent to the PMP module for PMP and PMA checks. It transitions to the mem_req state in the next cycle. The PMP module needs to return whether an access fault occurred during the physical address check in the same cycle.
  • mem_req: Based on the results of the PMP and PMA checks, if the check result indicates an access fault, it enters the check_pte state; otherwise, it sends a request to memory. It continues to wait in the mem_req state until the handshake with memory is successful, indicating that the request has been successfully sent, after which it enters the mem_resp state.
  • mem_resp: In the mem_req state, the Hypervisor Page Table Walker has already sent a PTW request to memory. In the mem_resp state, the Hypervisor Page Table Walker waits for a response from memory. Upon receiving a response from memory and successful handshake between memory and Hypervisor Page Table Walker, it enters the check_pte state.
  • check_pte: This state evaluates the current query situation to decide the next action. This state handles the following situations:
    1. An accessfault or pagefault occurs, returning to PTW or LLPTW.
    2. The page table returned by memory is a leaf node, returning directly to PTW or LLPTW.
    3. If it is not a leaf node, the physical address is sent to the PMP module for PMP&PMA checks, and the state transitions to mem_req, repeating the process described above.

Interface Timing

Similar to PTW, no further details are provided.