Level 3 Module: Miss Queue

Miss Queue refers to the following module:

• L2TlbMissQueue missQueue

Design Specifications

1. Buffer requests waiting for resources

Functionality

Buffering requests waiting for resources

The essence of Miss Queue is a queue, receiving requests from Page Cache and Last Level Page Table Walker, and sending them to Page Cache. When Page Cache sends a request to PTW, but the request is isFirst or PTW is busy, the request is sent to Miss Queue. When Page Cache sends a request to LLPTW, but LLPTW is busy, the request is sent to Miss Queue.

Overall Block Diagram

The overall structure of Miss Queue is relatively simple and will not be elaborated upon further. For the connection relationship between Miss Queue and other modules within the L2 TLB, please refer to section 5.3.3.

Interface Timing

The essence of Miss Queue is a queue, and the interface timing is relatively simple and will not be elaborated upon further.