Level 3 Module: Page Table Walker

Page Table Walker refers to the following module:

• PTW ptw

Design Specifications

1. Supports accessing the first two levels of page tables
2. Supports sending PTW requests to memory
3. Supports forwarding PTW requests to LLPTW
4. Supports sending refill signals to Page Cache
5. Supports exception handling
6. Supports two-stage address translation

Functions

Accessing the First Two Levels of Page Tables

The essence of the Page Table Walker is a state machine that accesses the page table level by level using the virtual address to obtain the physical address. The Page Table Walker can only process one request at a time and can access at most the first two levels of the page table, indicating limited memory access capability. The behavior of the Page Table Walker in virtual-to-physical address translation is similar to the manual description. Before accessing memory, a PMP check is required on the physical address to be accessed. If the PMP check fails, it returns directly; otherwise, it sends a PTW request to memory or llptw. With the addition of the H extension, the PTW is still responsible for the translation of the first two levels of the first stage. The physical addresses calculated in the first two levels of translation must undergo a second stage address translation to obtain the true physical address before memory access can occur. It also supports scenarios with only second-stage translation and only first-stage translation. When memory returns a page table entry, a PMP check is also required. The Page Table Walker will continue the above operations until one of the following three situations occurs:

1. A leaf node (large page) is accessed, and it returns directly to L1 TLB (if it is an allStage translation, a second stage translation is performed before returning).
2. A level two page table is accessed, and it is returned to LLPTW, which handles the access to the last level of the page table.
3. A Page fault or Access fault occurs during access.

Sending PTW Requests to Memory or llptw

When the Page Table Walker accesses the first two levels of the page table, it needs to send a PTW request to memory. When the access to the first two levels of the page table is completed, it needs to send a PTW request to llptw. The requests sent by PTW to memory, the requests sent by LLPTW to memory, and the requests sent by HPTW to memory need to pass through arbitration before being sent to memory. The TileLink protocol's A and D channel source signals are used to mark whether the request originates from PTW, LLPTW, or HPTW.

Sending Refill Signals to Page Cache

When the PTW request sent by the Page Table Walker to memory receives a reply, it will send a refill request to the Page Cache. Memory will write back the returned page table entry into the Page Cache, but the Page Table Walker needs to provide additional information such as the virtual page number of the page table, the page table level, and the page table type. Depending on whether the translation request is a two-stage address translation request, the page tables filled into the Page Cache are categorized as noS2xlate and onlyStage1.

Exception Handling Mechanism

Access fault exceptions may occur in the Page Table Walker and will be delivered to the L1 TLB. The L1 TLB will handle it based on the source of the request. Refer to Section 6 of this document: Exception Handling Mechanism.

Overall Block Diagram

The essence of the Page Table Walker is an s/w state machine divided into request and response events. Each state is represented by a pair of request and response events. Here, a common state machine state transition diagram and transition relationships are used for easier understanding. For the connection relationship between the Page Table Walker and other modules in the L2 TLB, refer to Section 5.3.3.

The state machine transition diagram is shown in 此图.

Page Table Walker State Machine Transition Diagram

To clearly represent the states, different types of requests are divided into two types of state machines, and their transition diagrams are drawn separately.

For the noS2xlate or onlyStage1 request state machine (left side of the figure above), the description of each state is as follows:

• idle: The initial state of the Page Table Walker. After the PTW accepts a request, it enters the pmp check state.
• pmp check: In this state, the accessed physical address is sent to the PMP module for PMP and PMA checks. In the next cycle, it enters mem req. The PMP module returns the check result (whether an access fault occurred) in the same cycle.
• mem req: Based on the check result, if an access fault occurs, it directly enters the final check state check pte (indicated by the mem_addr_update signal being valid in the chisel code). If no access fault occurs, a memory access request is sent, and it enters the mem resp state.
• mem resp: This state waits for memory to return. After returning, it enters the check pte state.
• check pte: In this state, the current request is checked to decide the next action:
  1. If a leaf node is not found and no access fault occurred, and the current level is the first level page table, it transitions to the mem req state.
  2. If an access fault occurred, it returns directly to L1TLB, and the state transitions to idle.
  3. If a level two page table is found and it is not a leaf node, it is sent to llptw.
  4. If a leaf node (large page) is found, it is returned to L1TLB.

For allStage and onlyStage2 requests:

• idle: After receiving these two types of requests, it enters the hptw req state and directly starts the second stage translation.
• hptw req: Sends a second stage translation request to L2TLB. After sending, it enters the hptw resp state.
• hptw resp: Waits for the hptw request to return. After hptw returns, if the current request is an onlyStage2 request, it directly enters the check pte state; otherwise, it enters the pmp check state.
• pmp check: In this state, the accessed physical address is sent to the PMP module for PMP and PMA checks. In the next cycle, it enters mem req. The PMP module returns the check result (whether an access fault occurred) in the same cycle.
• mem req: Based on the check result, if an access fault occurs, it directly enters the final check state check pte (indicated by the mem_addr_update signal being valid in the chisel code). If no access fault occurs, a memory access request is sent, and it enters the mem resp state.
• mem resp: This state waits for memory to return. After returning, it enters the check pte state.
• check pte: If it is a non-onlyStage2 request (i.e., allStage), and a leaf node is not found and no access fault occurred, it enters the hptw req state. If a leaf node is not found and the level is already a level two page table, the request is sent to llptw. If the last s2xlate signal is valid at this time, it indicates that a second stage address translation is required before returning (onlyStage2 requests do not need this). If a leaf node is found at this time and the last address translation has also been performed, it is returned to L1TLB.

It should be noted that the PTW also handles allStage requests that hit in stage 1. After such a request enters, it performs a second stage translation and then returns directly to L1TLB.

Interface List

The signal list of the Page Table Walker can be summarized into the following categories:

1. req: The Page Table Walker only accepts requests from the Page Cache and must meet the corresponding conditions. Refer to the introduction to Page Cache in Section 5.3.7.
2. resp: If the Page Table Walker accesses a large page or a PMP&PMA check error occurs, it returns the relevant information to the L1 TLB.
3. llptw: If the Page Table Walker has only the last level of the page table left to access or a PMP&PMA check error occurs, it returns the relevant information to the L1 TLB.
4. mem: Interaction with memory when the Page Table Walker needs to access memory, involving req and resp. The handshake signals between the Page Table Walker and memory are also used to control the state machine transitions of the Page Table Walker.
5. pmp: Interaction between the Page Table Walker and the PMP module for PMP and PMA checks.
6. refill: After the Page Table Walker obtains the result from memory access, it needs to write back the returned result from memory and relevant information into the Page Cache.
7. hptw: After the Page Table Walker obtains the guest physical address, it sends a second stage translation request to L2TLB. L2TLB will send the query result back to PTW.

Refer to the interface list document for details.

Interface Timing

The Page Table Walker interacts with other modules in the L2 TLB using the valid-ready method. The signals involved are relatively numerous and there are no particularly critical timing relationships, so they will not be elaborated upon further.