Level 3 Module Prefetcher

The Prefetcher refers to the following module:

• L2TlbPrefetch prefetch

Design Specifications

1. Supports the Next-line prefetching algorithm
2. Supports filtering duplicate historical requests

Functionality

Issuing Prefetch Requests

A prefetch request is issued when one of the following two conditions is met:

1. A Page Cache miss occurs.
2. A Page Cache hit occurs, but the hit is a prefetch entry.

The Prefetcher employs the Next-Line prefetching algorithm. The prefetch results are stored in the Page Cache and are not returned to the L1 TLB. Due to the Page Table Walker's weak memory access capability, prefetch requests do not enter the Page Table Walker or Miss Queue; they are directly discarded. When a prefetch request is only missing the last level page table, it can access the LLPTW. Additionally, a Filter Buffer has been added to the Prefetcher to filter duplicate prefetch requests.

Filtering Duplicate Historical Requests

To avoid wasting L2 TLB resources on duplicate requests and to improve Prefetcher utilization, when issuing prefetch requests under the two conditions described in Section 5.3.11.2, it is determined whether a prefetch request for the same address has already been issued. If it has, the newly received prefetch request is discarded. The current Prefetcher module filters the most recent 4 requests.

Overall Block Diagram

The overall block diagram of the Prefetcher is shown in 此图. When a Page Cache miss occurs or a Page Cache hit occurs where the hit is a prefetch entry, a prefetch request is generated. Duplicate prefetch requests can be filtered via the Filter Buffer.

Overall Block Diagram of the Prefetcher

Interface Timing

The Prefetcher is a next-line prefetcher, and its interface timing is relatively simple, so it will not be elaborated on here.